This invention relates in general to semiconductor devices, and, in particular, to an improved saturable charge gallium arsenide gate field effect transistor.
A semiconductor-insulator-semiconductor field-effect transistor with a gallium arsenide gate is described in, "A GaAs Gate Heterojunction FET", P. M. Solomon, et al., IEEE Electron Device Letters, Volume EDL-5, No. 9, September 1984. That transistor has a heavily doped. n-type gallium arsenide gate with an undoped aluminum gallium arsenide gate insulator disposed on an undoped gallium arsenide layer. Sources and drains are fabricated from n-doped, ion-implants. Compared to a silicon based MOSFET, the gallium arsenide gate FET has a lower threshold voltage, a higher speed of operation due to an extraordinary electron mobility at low temperatures, and a low power supply voltage requirement.
However, the relatively low gate voltage has certain drawbacks. In particular, the low gate voltage results in an appreciable gate leakage current. The leakage current is particularly significant in low power dissipation circuits such as complimentary and memory cells. In such cells, it is desirable to have very thin insulating layers of aluminum gallium arsenide in order to yield a higher transconductance. It is also desirable to operate devices with larger gate voltages. In both cases, the thinner layer of aluminum gallium arsenide and the increased operating voltage on the gate increases the undesired leakage current.
So, it is desirable to have an FET as described above with a gate structure that operates at higher voltages and has less leakage current. It is particularly desirable to have such a device without any compromise in the speed or performance of the GaAs gate FET.